Gen-Z Consortium Preps High-Speed Memory Interconnect

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    Sometime shortly after the turn of this decade, IT organizations should witness the arrival of servers capable of maximizing a new generation of high-speed nonvolatile memory that is supposed to begin arriving next year.

    A Gen-Z Consortium formed by AMD, ARM, Cavium Inc., Cray, Dell EMC, Hewlett Packard Enterprise (HPE), Huawei, IBM, IDT, Lenovo, Mellanox Technologies, Micron, Microsemi, Red Hat, Samsung, Seagate, SK hynix, Western Digital Corporation, and Xilinx is working on a new high-speed interconnect based on a specification due out later this year.

    Gen-Z Consortium president Kurtis Bowman, who is also the director of server solutions in the office of the CTO at Dell EMC, says that specification will then be used to create a new open memory interconnect in the form of a proof-of-concept in 2017. Production of the new memory connect would then move forward in 2018, resulting in servers using that memory bus most likely arriving by 2020, says Bowman.

    Capable of supporting several hundred GB/s of bandwidth to provide access to sub-100 nanosecond memory such as the 3D X Point memory technology that Intel and Micron are developing, the memory interconnect technology being proposed by the Gen-Z consortium is at the very least intriguing because it provides a crucial missing piece in the quest to shrink the data center. As more primary storage moves into the memory, the overall density of the data center environment can increase dramatically because both the number of physical servers and storage devices can theoretically be sharply reduced.

    Bowman says the new memory interconnect will be designed to support both multiple types of processors and nonvolatile memory. Of course, that may also account for why Intel has not yet elected to join the effort. Given its investment in 3D X Point, it’s probable that Intel is investing in developing its own advanced memory interconnect technology. Intel is also absent from an OpenCAPI Consortium that has pledged to develop open interfaces by 2017 that more tightly couple different classes of co-processors with main CPUs. That effort is being led by AMD, Dell EMC, Google, Hewlett Packard Enterprise, IBM, Mellanox Technologies, Micron, NVIDIA and Xilinx.

    The one thing that everybody does seem to agree on is that multicore processors and advanced forms of nonvolatile memory will soon transform IT.

    “Faster memory connects will turn on the innovation ignition,” says Ron Noblett, vice president of advanced architecture development in the CTO Organization of HPE. “The amount of memory available per core today is actually less than it was in 2003.”

    Whatever form that innovation takes, the one thing IT organizations can count on is that the data center as a whole will not only be a lot smaller in terms of space and energy consumed than today; it will also provide orders of magnitude more performance.

    Mike Vizard
    Mike Vizard
    Michael Vizard is a seasoned IT journalist, with nearly 30 years of experience writing and editing about enterprise IT issues. He is a contributor to publications including Programmableweb, IT Business Edge, CIOinsight and UBM Tech. He formerly was editorial director for Ziff-Davis Enterprise, where he launched the company’s custom content division, and has also served as editor in chief for CRN and InfoWorld. He also has held editorial positions at PC Week, Computerworld and Digital Review.

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