Saving Energy One Chip at a Time

Arthur Cole
Slide Show

New Tips to Improve Energy Management

Ways software can be used to improve overall data center energy use.

Lessening the power draw in the data center is more than just a nice thing to do for the environment - it's sound economics.

The IT industry has been fortunate in this regard considering that, for the first time in its history, low-power operations are coinciding with, and sometimes even fostering, improved performance.

Not all of this efficiency is taking place on the virtual level, however. New generations of low-power components and chip-level systems are driving server, networking and storage operations to new performance levels even as they dole out wattage ever more parsimoniously.

A key example is the new line of ARM processors poised to take on advanced data environments. ARM Holdings' new ARMv8 architecture is the first to include a 64-bit instruction set, putting it in league with the top enterprise offerings from Intel and AMD. This allows firms like Calxeda to design increasingly stingy SoCs like the new EnergyCore, which operates at 5 watts on average but can drop to as little as 1.5 watts for some applications and even .5 watts while idle. At the same time, the design provides 4 MB of L2 cache and an integrated fabric switch for 10 GbE networks. HP is already working on a Calxeda-based architecture that could shrink performance of a 700-server farm down to a single rack.

At the same time, IDT is looking to improve server and storage system efficiency with a new low-power DDR3 register. The SSTE32882KB1 (once you get down to the memory module, you can forget about cutesy brand names) is said to reduce the power draw by 20 percent when active and 40 percent when idle, drastically cutting the overhead of a standard RDIMM. When paired with some of the new low-power DRAMs, the device can generate a 15 percent reduction in overall power consumption.

Network devices are likely to see higher levels of efficiency as well with chipsets like Cavium Inc.'s Nitrox III security and compression device. The set includes from 16 to 64 specialty RISC cores along with a string of compression engines to provide up to 200,000 SSL ops, 40 Gbps SSL and 20 Gbps compression processing on top of a virtualization engine with a PCIe Gen 2 16-lane interface, all within a power envelope equal to current multichip designs. The unit is targeted at Application Delivery Controllers, Cloud Server Offload devices, WAN optimization and standard routers, switches and servers.

All of this activity on the chip level virtually guarantees that enterprises will become more power-efficient regardless of whether they implement a formal energy-reduction strategy or not. Even if the new technology proves to be more expensive than higher-power alternatives, the TCO should work out strongly in its favor as data loads continue to mount.

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