PCIe 3.0 in the Final Stages

Arthur Cole

The drive for greater data center throughput usually focuses on the network. Ethernet, InfiniBand, Fibre Channel and the overall network fabric are the main drivers to greater performance.

On the component level and server interface though, a similar evolution is taking place-one that is about to take a significant leap forward in the form of the new PCI-Express 3.0 standard. The new spec is due out in November and it represents a doubling for performance over the 2.0 standard, which was itself a giant leap forward from the original PCI format.

As it stands, PCI 3.0 will bump the data rate from the current 5 gigatransfers per second (GTps) to 8. However, the bigger news is that encoding is due to increase from the current 8- and 10-bit format to 128- and 130-bit when the system is functioning at a full 8 GTps. It also features a new Dynamic Feedback Equalization (DFE) mechanism that improves signal-to-noise (S/N) ratios through an innovative time-variant adaptation process.

Sharp eyes may note that a jump from 5 GTps to 8 GTps is not exactly a doubling of performance. However, it must be noted that the 2.0 spec's 5 GTps included a 20 percent performance overhead to accommodate the 8-/10-bit encoding. The new standard offers a much more efficient coding scheme that leaves virtually the entire bandwidth free for signal processing.

As usual with the standards-setting process, the format has been locked down for long enough that initial products are already hitting the channel. Pericom Semiconductor just announced a new set of 3.0-compatible switch solutions in its ReDriver line, including a signal conditioner and clock-generation and buffering devices. Signal conditioning at 8 GTbs is expected to be a more crucial requirement for future 3.0 devices due to the faster throughput.

Meanwhile, Agilent Technologies is already out with a number of 3.0 physical and protocol layer test solutions, including a 32 GHz oscilloscope and a new digital test console The scope is a Windows-based device that features a 30 GHz probing system and an application-specific measurement software kit optimized for the higher transfer speed. The test console features a x1 through x16 protocol analyzer and a complete exerciser solution.

These are just the initial droplets of what is likely to become a flood of PCIe 3.0 systems in the first quarter of next year. In the meantime, it still pays to keep up with PCIe 2.0 technology, considering it provides a foundation for high-speed interconnects within the data center-and the 3.0 standard is fully compatible with both the 2.0 and original PCIe formats.

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