More details are starting to emerge on Intel's new shared bus architecture, currently known as the Common Systems Interconnect (CSI) but rumored to be redubbed QuickPath by the time of its launch next year. Naturally, everyone is keen to know whether Intel has developed a truly innovative approach to multicore processing and whether it can stack up against AMD's HyperTransport.
The most detailed description of CSI comes from David Kanter, editor of the Real World Technologies web site, who compiled a lengthy overview of what Intel has in mind based on the company's patent applications and some inside sources. Kanter describes a number of implementations designed to accommodate integrated memory controllers and distributed shared memory for just about all upcoming Core, Xeon and Itanium lines coming down the pike.
Two key products ripe for a new bus technology are the high-end Xeons and the Tukwila Itaniums aimed at the high-performance computing space, says HPCWire. Current versions of both chips use hefty on-chip cache banks to overcome the limitations of the separate front side bus and memory controller design, so a more elegant design should push both past the today's Opteron devices and put them in league with the Power and Sparc chips.
Still, having had the jump on Intel for the past few years, don't expect AMD to stay idle. The HyperTransport architecture is likely to be the mainstay for the Opteron well into the future, but its implementation is likely to change. The upcoming dual quad Sandtiger processor will be the first to sport the HT 3.0 spec, which tops out at 2.6 GHz and offers a bandwidth of 41.6 GBps, double that of HT 2.0. That's compared to an expected 24-32 GBps range for CSI. The Sandtiger will also provide four HT links per core, albeit at the cost of a larger socket.
The thing to keep in mind is that Intel isn't talking about a commercial release of CSI until late next year, which could very well be pushed back to 2009 depending on how development is going. That means AMD still has plenty of time to shore up its lead in high-end multisocket designs.