A Plan for Multicore Memory

Arthur Cole

CPUs offer multicore processing, so why can't memory chips do the same thing?


That's the question that bothered cryptographer Joseph Ashwood before he came up with what is being described as a new architecture for multicore memory. The so-called Ashwood Architecture uses a smart controller alongside a memory array on a single chip to provide for hundreds of concurrent processes. The design is said to offer 16 GBps and shares some similarities with Fibre Channel.


Ashwood says he has a patent pending, even though he has yet to put the design on actual silicon. Among some of the real-world concerns is whether the overhead needed for parallel access will slow performance more than the parallelism will enhance it.


Still, it offers a potentially significance to the networking impact of multicore CPUs. After all, what good is it to process data faster if it can only trickle out of memory?

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